Title :
The role of timing verification in layout synthesis
Author :
Benkoski, Jacques ; Strojwas, Andrzej J.
Author_Institution :
Carnegie Mellon University
Keywords :
Circuit synthesis; Design automation; Equations; Integrated circuit layout; Integrated circuit synthesis; Libraries; Logic; Microelectronics; Process design; Timing;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
