Title :
A fast physical constraint generator for timing priven layout
Author_Institution :
IBM Thomas J. Watson Research Center
Keywords :
Added delay; Capacitance; Delay effects; Design optimization; Information analysis; Logic; Performance analysis; Timing; Wire; Wiring;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
