DocumentCode

2172836

Title

A fast physical constraint generator for timing priven layout

Author

Luk, Wing K.

Author_Institution

IBM Thomas J. Watson Research Center

fYear

1991

fDate

21-21 June 1991

Firstpage

626

Lastpage

631

Keywords

Added delay; Capacitance; Delay effects; Design optimization; Information analysis; Logic; Performance analysis; Timing; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1991. 28th ACM/IEEE

Conference_Location

IEEE

Print_ISBN

0-89791-395-7

Type

conf

Filename

979789