A Novel Smart Temperature Sensor: Extracting Run-time Temperature within SRAM Cells

In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple SRAM cells simultaneously ever since it has becoming one of the highest heat dissipation members subsequent to the increase demands in density and speed for many applications. By optimizing the bit-line loads with the pull-down transistors, the range of the voltage variations correspond to temperature scale can be quantified for feedback system. The mechanism will beneficial the SRAM from possible soft-thermal errors, which is hold by its Static Noise Margin(SNM), also improve the reliability(eg. hard-thermal errors) of the system. The proposed methods fulfilled those needs to incorporate a sensor closer to defect area with minimized hardware overhead. Correspondingly, we did not cause anything that worsens the 6T-SRAM designs, such as SNM and the minimal sizing of SRAM cell requirement.