DocumentCode :
2173255
Title :
Effects of lead bonding process on reliability of chip scale package
Author :
Lee, Yeong J. ; Eyre, Matthew W.
Author_Institution :
Electron. Packaging Mater. Dev., Dow Corning Corp., Midland, MI, USA
fYear :
2000
fDate :
2000
Firstpage :
1392
Lastpage :
1397
Abstract :
An integrated circuit (IC) package has become smaller and its profile becomes lower as new chip scale packaging (CSP) designs have been introduced. A new design of packages demands new materials and optimization of manufacturing processes to enhance reliability of the package. A compliant layer in Tessera´s μ-BGA(R) package is a crucial component to increase solder ball reliability in the board level assembly. The compliant layer can reduce damage to the solder balls, which is induced by mismatch of the coefficient of thermal expansion (CTE) between Si die and the printed circuit board (PCB). Silicone elastomer is one of the best candidate for the compliant layer due to its low modulus and low moisture absorption. While the colder ball reliability in the μ-BGA package is significantly improved due to its unique design and optimal materials set, fatigue damage can be imposed on beam leads inside of the package during thermal cycling. To reduce the damage in the package, an optimal lead (or beam lead) bonding process becomes critical for flex circuit interposer type of CSP designs including μ-BGA. Three dimensional (3D) Finite Element Analysis (FEA) of the lead bonding and subsequent thermal cycling, is conducted to show effects of designs of the lead (dimensions and shapes) as well as the lead bonding process parameters. Several different loci of a bond tool motion are numerically simulated to determine optimal lead bonding parameters based on the calculated damage accumulated in the deformed shape of leads during the lead bonding process followed by the thermal cyclings
Keywords :
ball grid arrays; chip scale packaging; fatigue; finite element analysis; lead bonding; reliability; soldering; chip scale package; compliant layer; fatigue damage; flex circuit interposer; integrated circuit package; lead bonding; micro-BGA package; numerical simulation; silicone elastomer; solder ball reliability; thermal cycling; three-dimensional finite element analysis; Assembly; Bonding processes; Chip scale packaging; Design optimization; Integrated circuit packaging; Integrated circuit reliability; Lead; Manufacturing processes; Materials reliability; Shape;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-5908-9
Type :
conf
DOI :
10.1109/ECTC.2000.853391
Filename :
853391
Link To Document :
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