A novel dynamic Vt circuit configuration

Summary form only given. It is a well known dilemma that as supply voltages are scaled lower, CMOS threshold voltages must also be scaled lower to maintain performance, leading to increased subthreshold leakage. One solution to mitigate the trade-off between high performance and low standby current is to modulate the threshold voltage by control of the well or body voltage, lowering the Vt in active mode and raising the Vt in standby. SOI is particularly suited for this because of the relatively low body capacitance, and the wider practical range of body vs well voltage. Developing circuit techniques to leverage this advantage may be critical to the successful commercialization of SOI technology. In this work, we propose a modification of the drain-to-body configuration that significantly reduces gate delay and is particularly appropriate for large drivers where a series of inverters is used. The basic configuration is to tie the drain of the transistor to the body of the transistor when the transistor is turned on, disconnecting it when the transistor is off. To evaluate the circuit design technique, simulations were run for a variety of configurations for three inverters in series