A third-order 1 MHz continuous-time sigma-delta modulator in a 130 nm CMOS process

This paper describes the design and implementation of a low-pass third-order single-loop single-bit continuous-time sigma-delta modulator (CT-SDM) in a 130 nm CMOS process. To reduce clock jitter effects and operational amplifiers requirements a non-return-to-zero (NRZ) digital-to-analog converter (DAC) pulse shape was employed. Post-layout simulation results indicate that the modulator achieves 56 dB of dynamic range, 57.31 dB of peak SNDR or 9.23 bits of effective resolution over a 1 MHz signal bandwidth with an oversampling ratio (OSR) of 64. The CT-SDM draws 5.91 mW from a 1.2 V power supply providing a figure-of-merit (FOM) of 4.93 pJ/conv. The CT-SDM core area is 0.31 mm² and the chip was manufactured and will be soon characterized.