Unconventional signal processing architecture for reconfigurable on-chip communication systems

Algorithms for digital communication systems can be represented via a set of specialized signal processing (SP) blocks. Hence, in the implementation of these algorithms, the interconnection among the processing blocks aggregates complexity to the design. Usually, these interconnections are made through specialized glue logic, Point-to-Point (P2P) interconnections, Bus or a Network on Chip (NoC). Furthermore, the communications industry´s trend is to move forward to Software Defined Radio (SDR) or reconfigurable communications SoC, which imposes hard constrains in the selected interconnection approach. Particularly, the management tasks directly influence the system´s performance. Therefore, it is important to study the decision of leaving this administration to a dedicated processor or to a general purpose processor. Here, a NoC-based architecture is proposed to overcome the management problem. A Feeder-Collector, that takes out the reconfiguration and managerial tasks from the main CPU is introduced. This architecture creates a HW-based library of SP functions which simplifies software applications, without sacrificing performance. Analytical and simulation results show that our proposal achieves a high performance and the lowest CPU´s load compared with P2P, Bus and conventional NoC interconnections.