Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis

The quest for technologies with superior device characteristics has showcased carbon nanotube field effect transistors (CNFETs) into limelight. Among the several design aspects necessary for today´s grail in CNFET technology, achieving functional immunity to carbon nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET design kit (DK) to realize a complete design flow from logic-to-GDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFET-based inverter can achieve gains, with respect to the energy-delay product (EDP) metric, of more than 4times in delay, 2times in energy/cycle and significant area savings (more than 30%) when compared to a corresponding CMOS inverter benchmarked with an industrial 65 nm technology.