A 12GHz programmable fractional-n frequency divider with 0.18um CMOS technology

In this paper, the design of programmable fractional-n frequency divider with 0.18pμm and TSMC process is presented. The proposed structure is based on Extended True-Single-Phase-Clock (E-TSPC) divider and created different fractions of the input frequency at the output node by changing the DC level of the input signal. The programmable frequency divider operates up to 12GHz and therefore, a 12GHz sinusoidal input voltage applies to produce simulation results. The circuit consumes power less than 1.44mW power from 1.8V supply voltage and have a small area occupation (about 22μm×42μm). The maximum value of linear noise at output node is about 440nV and the duty-cycle of output voltage is about 50%. The high-swing sinusoidal input voltage and 1pF load capacitance impact on the programmable structure have been investigated and new structure suggested under these conditions. Advanced Design System (ADS) used to produce simulation results and Ledit utilized for drawing layout.