VLSI implementation of gigabit ethernet with data compression and decompression

The project work entitled "VLSI IMPLEMENTATION OF GIGABIT ETHERNET WITH DATA COMPRESSION" is an attempt to design Ethernet MAC and the data compression and decompression can be added to get the data rate more than lGbps. Recently, Ethernet celebrated its twentieth anniversary. Over those years, the processing speed of the attached hosts has increased by several orders of magnitude, to the point where the relative bandwidth of a 10 Mbps Ethernet has fallen from more than adequate to support large enterprise networks (whose utilization were typically only a few percent, anyway), to marginally fast enough to support a single high performance desktop workstation. At the same time, the Ethernet standard has also evolved to incorporate new technology at the physical layers, including new media, new signaling methods, and support for higher data rates. However, the MAC layer protocols have remained essentially unchanged from the early days of undemanding applications running on large numbers of slow hosts. In this paper, we argue that it is time to review the MAC layer and incorporate advances made in the protocol performance field over the last twenty years. In this paper deals with the implementation of Ethernet MAC in FPGA kit.