Fault analysis for Field Programmable Gate Array (FPGA) using phase path method

The re-configurability of field programmable gate array´s (FPGA) plays an important role in reducing on-chip testing hardware relative to application specific integrated-circuits (ASICs). In general, fault coverage is directly related to the number and scope of test configurations that are created. To operate effectively, the specific location of the fault should be clearly identified. The fault coverage issue has been further complicated in recent years by the introduction of FPGA devices with millions of programmable switch points. This paper aims at fault detection and location in interconnects of an FPGA. The proposed testing scheme uses a test manager, which defines a part of the chip as pattern generator and the other half as response analyzer. The chip is reconfigured several times to cover all portions of interconnect. Testing is done in two phases, phase one involves several reconfigurations intended to detect various faults in the interconnect structure. Another phase involves extensively testing the complete interconnect structure for all possible faults namely configurable interconnection points stuck on, configurable interconnection points stuck off, wire stuck-at-1, wire stuck-at-0, two adjacent wires short, and wires open etc.