Communication Scheme Design for Parallel Architecture Implemented in a FPGA for Solution of Linear Equation Systems

This paper presents a communication scheme design with VHDL language for parallel array of processors implemented in a Field Programmable Gate Array (FPGA) for the solution of linear equation systems. The solution is performed using the division-free Gaussian elimination method. This algorithm was implemented in integrated processors in a FPGA Spartan 3 of Xilinx. The communication design uses read/write communication channels. These channels transmit the coefficients calculated with division free Gaussian elimination method from Processor Elements (PE) to another in the array of parallel architecture. Vertical channels are used for the columns onto the processor grid whereas horizontal channels are used for rows. A top-down design was used. The proposed architecture can handle IEEE 754 single and double precision floating-point data and the architecture is implemented in 240 identical processors.