Performance Estimation of a First-Order Sigma-Delta Modulator in a CMOS Image Sensor Using Behavioral Modeling

The system-on-chip of study is a proposed CMOS Image Sensor (CIS) architecture which includes: passive pixel array, digital switches for rows/columns and a first-order single-bit Sigma-Delta Modulator for every four columns. This paper presents the behavioral model of the Sigma-Delta Modulator, to estimate their performance in terms of Signal to Noise Ratio and Dynamic Range. The model starts with an ideal modulator, and then are added noise sources and nonlinear distortions, arose by the light source and the modulator non-idealities. All modeling was developed at system level. The performance obtained with the compartmental model showed good agreement with the temporal measurements obtained directly from CIS. This model allows determining the main noise sources that degrade the performance.