DocumentCode :
2174552
Title :
Gate sizing for large cell-based designs
Author :
Held, Stephan
Author_Institution :
Res. Inst. for Discrete Math., Univ. of Bonn, Bonn
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
827
Lastpage :
832
Abstract :
Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step. Slew targets are updated by an estimate of the local slew gradient. To demonstrate the effectiveness, we propose a new heuristic to estimate lower bounds for the worst path delay. On average, we violate these bounds by 6%. A subsequent local search decreases this gap quickly to 2%. This two-stage approach is capable of sizing designs with more than 5.8 million cells within 2.5 hours and thus helping to decrease turn-around times of multi-million cell designs.
Keywords :
application specific integrated circuits; delay systems; iterative methods; timing; delay budgets; discrete cell choices; discrete cell libraries; gate sizing algorithm; multimillion cell designs; sizing step; slew targets; timing models; turn-around times; two-stage approach; worst path delay; Application specific integrated circuits; Capacitance; Delay effects; Delay estimation; Iterative algorithms; Libraries; Mathematics; Pins; Solid modeling; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090777
Filename :
5090777
Link To Document :
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