Optimizing lateral HBT design by utilizing performance estimations

In this work, we concentrate on the fundamental relations for improving the HBT device performance by varying the layout and general transistor design parameters. With respect to the widely known analytical equations for the HBT device behavior, estimations have been made to predict the optimum design. These estimations have been proven by fabricating a large number of different designs on the same wafer. In this paper, the dependence on emitter length and width dimensions will be in focus, as well as general orientation issues