DocumentCode :
2174576
Title :
Optimizing lateral HBT design by utilizing performance estimations
Author :
Driesen, J. ; Topaloglu, S. ; Tegude, F.J.
Author_Institution :
Dept. of Solid State Electron., Duisburg Univ.
fYear :
2005
fDate :
8-12 May 2005
Firstpage :
441
Lastpage :
444
Abstract :
In this work, we concentrate on the fundamental relations for improving the HBT device performance by varying the layout and general transistor design parameters. With respect to the widely known analytical equations for the HBT device behavior, estimations have been made to predict the optimum design. These estimations have been proven by fabricating a large number of different designs on the same wafer. In this paper, the dependence on emitter length and width dimensions will be in focus, as well as general orientation issues
Keywords :
heterojunction bipolar transistors; semiconductor devices; optimizing lateral HBT design; transistor design parameter; Contact resistance; Design optimization; Equations; Etching; Frequency; Heterojunction bipolar transistors; Indium gallium arsenide; Indium phosphide; Optical buffering; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Indium Phosphide and Related Materials, 2005. International Conference on
Conference_Location :
Glasgow, Scotland
ISSN :
1092-8669
Print_ISBN :
0-7803-8891-7
Type :
conf
DOI :
10.1109/ICIPRM.2005.1517526
Filename :
1517526
Link To Document :
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