Design of an INS aided high dynamic GPS receiver

GPS receiver tracking loop will loose lock easily in high dynamic environments. The velocity of INS (inertial navigation system) aided GPS receiver may advance the tracking loop in a high performance and improve anti-jamming capability. In this paper, the design of FPGA and DSPs based software receiver is described. In this system, The INS processor is embedded in the GPS receiver, so the velocity of INS would be used to aid the receiver in tracking loop. This system consists of two parts, a front-end circuit and a digital signal processor circuit. The GPS satellite´s signal reaches the receivers through an antenna, and then is converted into IF signal (for intermediate frequency signal) by the front-end circuit, those signals enter the next stage of digital signal processing. Inertial signals shifts to signals processing stage through the serial port. Inertial navigation solution is finished in the receivers, and then loop aiding is achieved. The digital signal processer was composed of one FPGA and two DSPs, the FPGA was receiver´s correlation channel, one DSPs is GPS navigation processor the other is INS processor, the two DSPs communicate by their HPI interface. The experiment indicates that this design has a high performance positioning result, and is significant for the realization of deep coupled SINS/GPS integration.