A 0.35 μm 560 KG SOI/CMOS gate array using field-shield isolation technique

Summary form only given. SOI/CMOS devices have been developed not only for memory LSIs but also for logic LSIs. Some of the recent works include gate arrays having 220-320 K usable gates and operating at a 2.0 V supply voltage. As the history of bulk/CMOS devices indicate, the market will demand SOI/CMOS gate array to integrate more and more gates and operate at lower and lower supply voltages to reduce power consumption. This paper describes a 1.0 V 560 KG SOI/CMOS gate array using 0.35 μm partially-depleted transistors to meet this demand. The field-shield isolation technique stabilizes the body potential of transistors sufficiently to suppress the floating-body problems. Also the technique eliminates the leakage current flowing through the transistor edge to suppress the standby current under sub-threshold leakage-level