DocumentCode :
2175070
Title :
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
Author :
Vignon, A. ; Cosemans, S. ; Dehaene, Wim ; Marchal, P. ; Facchini, Marc
Author_Institution :
ESAT - MICAS Lab., K.U. Leuven, Leuven
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
929
Lastpage :
933
Abstract :
This paper presents a DRAM architecture that improves the DRAM performance/power trade-off to increase their usability on low power chip design using 3D interconnect technology. The use of a finer matrix subdivision and buffering the bitline signal at the localblock level allows to reduce both the energy per access and the access time. The obtained performances match those of a typical low power SRAM, while achieving a significant area and static power reduction compared to these memories. The 128 kb memory architecture proposed here achieves an access time of 1.3 ns for a dynamic energy of less than 0.2 pJ per bit. A localized refresh mechanism allows gaining a factor of 10 in static power consumption associated with the cell, and a factor of 2 in area, when compared with an equivalent SRAM.
Keywords :
DRAM chips; integrated circuit interconnections; low-power electronics; power consumption; 3D interconnect technology; DRAM architecture; SRAM memories; bitline signal buffering; cache system; low power chip design; matrix subdivision; memory architecture; static power consumption; time 1.3 ns; Capacitors; Clocks; Degradation; Delay; Energy consumption; Logic; Random access memory; Routing; Stability; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090798
Filename :
5090798
Link To Document :
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