A novel memory hierarchy with multi-channel for fast packet buffers

High performance routers require fast packet buffers to hold packets awaiting transmission[1]. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements[2]. In this paper, we introduce a particular memory hierarchy as packet buffer architecture which consists of multiple, independent memory channels of large, slow, low cost DRAMs coupled with small, fast SRAMs. Experiment results shows that this approach improved the memory bandwidth utilization in network processor remarkably.