• DocumentCode
    2175543
  • Title

    Design and implementation of scalable, transparent threads for multi-core media processor

  • Author

    Kodaka, Takeshi ; Sasaki, Shunsuke ; Tokuyoshi, Takahiro ; Ohyama, Ryuichiro ; Nonogaki, Nobuhiro ; Kitayama, Koji ; Mori, Tatsuya ; Ueda, Yasuyuki ; Arakida, Hideho ; Okuda, Yuji ; Kizu, Toshiki ; Tsuboi, Yoshiro ; Matsumoto, Nobu

  • Author_Institution
    Center for Semicond. Res. & Dev., Toshiba Corp., Kawasaki
  • fYear
    2009
  • fDate
    20-24 April 2009
  • Firstpage
    1035
  • Lastpage
    1039
  • Abstract
    In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the number of cores, and the application program is not affected by the actual number of cores. For the performance efficiency, we designed the threads so that they do not suspend and that they do not start their execution until the data necessary for them are available. We implemented our design using three modules: the dependency controller, which controls dependencies among threads, the thread pool, which manages the ready threads, and the thread dispatcher, which fetches threads from the pool and executes them on the core. Our design and implementation provide efficient thread scheduling with low overhead. Moreover, by hiding the actual number of cores, it realizes transparency. We confirmed the transparency and scalability of our scheme by applying it to the H.264 decoder program. With this scheme, modification of application program is not necessary even if the number of cores changes due to disparate requirements. This feature makes the developing time shorter and contributes to the reduction of the developing cost.
  • Keywords
    microprocessor chips; multi-threading; parallel processing; processor scheduling; H.264 decoder program; dependency controller; multicore media processor; multicore processor; parallelization scheme; thread dispatcher; thread pool; thread scheduling; CMOS logic circuits; Costs; Decoding; Hardware; Multicore processing; Parallel processing; Pipeline processing; Scalability; VLIW; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
  • Conference_Location
    Nice
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-3781-8
  • Type

    conf

  • DOI
    10.1109/DATE.2009.5090816
  • Filename
    5090816