Minimizing Thermal Disparities during Placement in 3D ICs

During the Computer Aided Physical Design Cycle and specifically for high-performance VLSI circuits, on-chip power density plays a major role. The catalyst factors are increased scaling of technology, increasing number of components, higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entails the stacking of multiple active layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of each of the active layers is not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer to ensure an efficient heat dissipation of the whole chip. Experimental results on randomly generated and standard MCNC and ISPD benchmark instances are quite encouraging.