DocumentCode
2175823
Title
Design of single-ended SRAM with high test coverage and short test time
Author
Wu, Chi-Feng ; Wang, Chua-Chin ; Hwang, Rain-Ted ; Kao, Chia-Hsiung
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
292
Abstract
The advantages of low power dissipation and smaller chip area for single-ended SRAM are well known. In this paper we present the configuration and the test strategy of a single-ended six-transistor SRAM. The benefits of short test time, no retention test and high test coverage are verified. The goal of high quality control and short test time of full CMOS SRAM test can be achieved
Keywords
CMOS memory circuits; SRAM chips; integrated circuit testing; full CMOS SRAM test; high test coverage; low power dissipation; short test time; single-ended SRAM; six-transistor SRAM cell; static RAM; test strategy; Bridge circuits; Circuit faults; Circuit synthesis; Circuit testing; Costs; Decoding; Electrical fault detection; Fault detection; Power supplies; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706915
Filename
706915
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