• DocumentCode
    2175902
  • Title

    A portable and fault-tolerant microprocessor based on the SPARC v8 architecture

  • Author

    Gaisler, Jiri

  • Author_Institution
    Eur. Space Agency, Noorwijk, Netherlands
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    409
  • Lastpage
    415
  • Abstract
    The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32 bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on-chip EDAC, parity, pipeline restart, and forced cache miss. The first prototypes were manufactured on the Atmel ATC35 0.35 μm CMOS process, and subjected to heavy-ion fault-injection at the Louvain Cyclotron. The heavy-ion tests showed that all of the injected errors (>100,000) were successfully corrected without timing or software impact. The device SEU threshold was measured to be below 6 MeV while ion energy-levels of up to 110 MeV were used for error injection.
  • Keywords
    fault tolerant computing; instruction sets; ion beam effects; microprocessor chips; 0 to 110 MeV; 0.35 micron; 32 bit; Atmel ATC35 CMOS process; LEON-FT processor architecture; Louvain Cyclotron; SPARC V8 instruction set; TMR registers; device SEU threshold; error injection; forced cache miss; heavy ion fault injection; on-chip EDAC; parity; pipeline restart; portable fault-tolerant microprocessor; transient SEU error tolerance; CMOS process; Cyclotrons; Fault tolerance; Manufacturing processes; Microprocessors; Pipelines; Prototypes; Registers; Software prototyping; Software testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Systems and Networks, 2002. DSN 2002. Proceedings. International Conference on
  • Print_ISBN
    0-7695-1101-5
  • Type

    conf

  • DOI
    10.1109/DSN.2002.1028926
  • Filename
    1028926