A simplicial method for the simulation of transistor shorts in CMOS logic gates

Author

Lin, Hung-Jen ; Milor, Linda

Author_Institution

Maryland Univ., College Park, MD, USA

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

300

Abstract

CMOS logic gates in the presence of gate-to-drain or gate-to-source shorts generally depend on electrical-level simulators such as SPICE to predict the circuit behavior which is required for the purpose of fault simulation. In the light of a wide variety of unintended networks caused by transistor shorts, the use of SPICE can be very computationally intensive. In this paper, a simplified technique for characterizing the static responses of faulty CMOS gates is presented. Example circuits are used to demonstrate the feasibility of the method. The results indicate that computational time can be reduced by a factor of 10 to 100 in comparison to SPICE simulation

Keywords

CMOS logic circuits; circuit analysis computing; fault diagnosis; logic gates; CMOS logic gates; computational time reduction; faulty CMOS gates; gate-to-drain shorts; gate-to-source shorts; static responses; transistor shorts; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Logic gates; Logic testing; Predictive models; SPICE; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706918

Filename

706918