ASIC packaging challenges with high speed interfaces

Author

Na, Nanju ; Audet, Jean

Author_Institution

IBM Syst. & Technol. Group, Essex, VT, USA

fYear

2008

fDate

10-12 Dec. 2008

Firstpage

20

Lastpage

23

Abstract

Networking speed is exploding as demanded with technology advancements and industry chip technology is evolving with rapidly increasing serial link data rates with high link integration for higher aggregate bandwidth and shrinking chip area and interface dimensions of devices. However, a large development speed gap between chip technologies and package technologies places great packaging challenges for high speed link applications where package wireability is driven by high frequency performance requirements. This paper discusses packaging challenges of high speed link applications with cost-performance tradeoffs in the technology trend.

Keywords

application specific integrated circuits; high-speed integrated circuits; integrated circuit packaging; semiconductor device packaging; ASIC packaging; aggregate bandwidth; chip area shrinkage; high speed interfaces; package wireability; serial link data rates; Application specific integrated circuits; Conductors; Costs; Frequency; Isolation technology; Manufacturing; Packaging; Routing; Space technology; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Packaging and Systems Symposium, 2008. EDAPS 2008. Electrical Design of

Conference_Location

Seoul

Print_ISBN

978-1-4244-2633-1

Electronic_ISBN

978-1-4244-2634-8

Type

conf

DOI

10.1109/EDAPS.2008.4735988

Filename

4735988