Title :
Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory
Author :
Chuang, Hao-Hsiang ; Wu, Shu-Jung ; Hong, Ming-Zhang ; Hsu, Darren ; Huang, Raphael ; Hsiao, Li Chang ; Wu, Tzong-Lin
Author_Institution :
Dept. of Electron. Eng. & Grad. Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS co-simulation of chip-package-PCB is important for the DDR3 circuit design.
Keywords :
chip scale packaging; circuit simulation; driver circuits; integrated memory circuits; printed circuit design; time-domain analysis; DDR3 high-speed memory; I/O interface; circuit design; off-chip driver circuits; power distribution system; power integrity chip-package-PCB co-simulation; time-domain simulation; Circuit simulation; Driver circuits; Frequency domain analysis; Frequency measurement; Impedance; Packaging; Power distribution; Power system modeling; Semiconductor device measurement; Time domain analysis;
Conference_Titel :
Advanced Packaging and Systems Symposium, 2008. EDAPS 2008. Electrical Design of
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-2633-1
Electronic_ISBN :
978-1-4244-2634-8
DOI :
10.1109/EDAPS.2008.4735991
