A wide input range analog multiplier for neuro-computing

Author

Al-Nsour, Mahmoud ; Abdel-Aty-Zohdy, Hoda S.

Author_Institution

Microelectron. Syst. Design Lab., Oakland Univ., Rochester, MI, USA

Volume

1

fYear

1997

fDate

3-6 Aug 1997

Firstpage

13

Abstract

A wide input range 4-quadrant analog multiplier design and its VLSI implementation are presented. The design is based on the squaring law operation of saturated NMOS transistors. The circuit is realized by using 12 NMOS and 2 PMOS transistors. The multiplier accepts two signed inputs in the range of ±4 V. The simulated corner frequency is found to be at 85 MHz. N-well 2 μm CMOS double metal process is utilized. It occupies 99×160 μm². Statistical linear regression showed that the multiplier has less than 1% overall error. By extending the input range and minimizing the silicon area, this design has high potential in evolving neuro-computing applications

Keywords

CMOS analogue integrated circuits; VLSI; analogue multipliers; neural nets; 85 MHz; N-well 2 μm CMOS double metal process; VLSI implementation; analog multiplier; input range; neurocomputing; saturated NMOS transistors; signed inputs; simulated corner frequency; squaring law operation; statistical linear regression; Circuit analysis; Design optimization; Intrusion detection; Laboratories; MOSFETs; Microelectronics; Neural networks; Neurons; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.666022

Filename

666022