DocumentCode :
2176365
Title :
Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design
Author :
Perry, Steve
Author_Institution :
Eur. Technol. Centre, Altera Corp., High Wycombe
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
1202
Lastpage :
1207
Abstract :
Model Based Design tools based around Simulink from The MathWorks are a popular technology for the creation of streaming DSP designs for FPGAs, since they offer the promise of rapid design exploration through immediate quantitative feedback of algorithm performance. Current tools typically use a library of components that reflect an explicit representation of the underlying FPGA device features. This is undesirable since the designer is forced to mix implementation and architecture, and leads to long design cycles and non-portable results. This paper shows that introducing techniques of high level synthesis allows a more elegant design at a higher level of abstraction. This results in fewer components needed for a design which translates into a faster design cycle, more portable designs and fewer defects. Pushbutton clock frequencies of up to 500 MHz are achieved without detailed knowledge of FPGA architectures. Although the capabilities described are embodied in the DSP Builder tool from Altera, this paper describes the technology involved rather than the details of the tools. Four major technologies are described: a latency-insensitive system representation, the module level internal representation with associated transformations, hardware retiming, and lastly a FIR filter design tool layered on top.
Keywords :
FIR filters; data flow graphs; digital signal processing chips; field programmable gate arrays; high level synthesis; integer programming; DSP Builder tool; FIR filter design tool; FPGA device; associated transformations; data flow graph; hardware retiming; high level synthesis; integer linear programming; latency-insensitive system representation; model based electronic design; module level internal representation; pushbutton clock frequency; Algorithm design and analysis; Clocks; Digital signal processing; Feedback; Field programmable gate arrays; Frequency; Hardware; High level synthesis; Libraries; Productivity; FIR Filter Design; FPGAs; High Level Synthesis; Model Based Design; Retiming; Technology Mapping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090845
Filename :
5090845
Link To Document :
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