The derivation of minimal test sets for combinational logic circuits using genetic algorithms

Author

Takhar, Jasbir S. ; Gilbert, Daphne J.

Author_Institution

Sch. of Sci. & Math., Sheffield Hallam Univ., UK

Volume

1

fYear

1997

fDate

3-6 Aug 1997

Firstpage

39

Abstract

To reduce the post-production cost of testing digital circuits, the derivation of minimal test sets is an important issue. The technique presented here applies a genetic algorithm to find minimal or near minimal test sets. The algorithm aims to minimise test sets that have been previously generated by an ATPG system and as such has been designed as a post-processor. The algorithm has been applied to a family of RISC (Reduced Instruction Set Computer) processors and a selection of ISCAS-85 benchmark circuits

Keywords

automatic testing; combinational circuits; genetic algorithms; integrated circuit testing; integrated logic circuits; logic testing; minimisation; ATPG system generated test sets; combinational logic circuits; digital circuit testing; genetic algorithms; minimal test sets; Algorithm design and analysis; Automatic test pattern generation; Circuit testing; Computer aided instruction; Costs; Digital circuits; Genetic algorithms; Logic testing; Reduced instruction set computing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.666028

Filename

666028