Design of a conditional sum adder based on multiple-valued logic

In order to improve the performance of arithmetic VLSI system, a kind of multiple-valued current-mode (MVCM) circuitry based on dynamic source-coupled logic is presented. Using the circuitry, a 4-quatrit quaternary adder based on conditional sum algorithm is proposed, which implements 8-bit addition operation. The use of conditional sum logic improves the speed of calculating. The design is evaluated by HSPICE simulation in 0.18μm CMOS technology with the supply voltage of 1.8V, and the simulation shows that its power dissipation is 2.8mW, the delay of sum is 0.689ns, and the transistor counts is 636. The combination of MVCM circuits and relevant algorithms seems to be a solution for high performance arithmetic and logic units in VLSI system.