Title :
Implementation and application of HDLC protocol based on FPGA in radar processing system
Author :
Zhifeng, Chen ; He, Chen ; Long, Pang
Author_Institution :
Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China
Abstract :
To meet the communications requirements of a wide band radar system, a HDLC controller based on FPGA was designed. The controller is set to idle mode when system reset or software reset occurs. The controller can be set to receiving or sending mode by software control. The special feature of the controller is especial low error rate and using very little hardware resource. Finally the controller was integrated into a wide band radar system, which proved the correctness and dependability of the controller.
Keywords :
field programmable gate arrays; protocols; radar signal processing; FPGA; HDLC protocol; high level data link control; idle mode; radar processing system; sending mode; software control; software reset; system reset; Process control; Radar; Radar signal processing; Random access memory; Receivers; Registers; Software; FPGA; HDLC; IP CORE; RS485Bus;
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
DOI :
10.1109/ICECC.2011.6066592
