A partition method in order to find embedded flip-flop structures in transistor circuits by applying graph theory concepts

Author

Tlelo-Cuautle, E. ; Sarmiento-Reyes, Arturo

Author_Institution

Inst. Tecnologico de Puebla

Volume

1

fYear

1997

fDate

3-6 Aug 1997

Firstpage

91

Abstract

This article presents a purely graph-oriented method in order to detect the presence of flip-flop-like structures embedded in BJT circuits. A first aim of this work is to obtain the admittance matrix of the circuit (2Q-representation) through the application of graph manipulations to the circuit-graph. Secondly, a method is presented that allows us to identify the graphs associated with a feedback structure (flip-flop). The resulting structure of the matrix allows us to carry out a partitioning method in order to detect the flip-flop structures in each sub-circuit

Keywords

bipolar logic circuits; circuit feedback; flip-flops; graph theory; logic partitioning; sequential circuits; BJT circuits; admittance matrix; embedded flip-flop structures; feedback structure; graph manipulations; graph theory concepts; partition method; sub-circuit; Admittance; Bipolar transistors; Circuits; Equations; Feedback; Flip-flops; Intelligent networks; Resistors; Vectors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.666041

Filename

666041