Statistical design techniques for yield enhancement of low voltage CMOS VLSI

Author

Tarim, Tuna B. ; Kuntman, H. Hakan ; Ismai, Mohammed

Author_Institution

Dept. of Electron. Eng., Istanbul Tech. Univ., Turkey

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

331

Abstract

Since random device/process variations do not scale down with feature size or supply voltage, statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. This is particularly true for low voltage analog ICs. This paper presents a robust design of a low voltage square-law CMOS composite cell, using statistical VLSI design tools. The Response Surface Methodology and Design of Experiment techniques were used as statistical tools. This paper shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs

Keywords

CMOS analogue integrated circuits; VLSI; design of experiments; integrated circuit design; integrated circuit yield; statistical analysis; VLSI; design of experiment; layout optimization; low voltage analog IC; response surface methodology; square-law CMOS composite cell; statistical design; yield; CMOS process; Circuits; Cost function; Design methodology; Electronic mail; Equations; Low voltage; Robustness; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706932

Filename

706932