A rail-to-rail input-range CMOS voltage comparator

Author

Chu, Wei-Shang ; Current, K. Wayne

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

1

fYear

1997

fDate

3-6 Aug 1997

Firstpage

160

Abstract

A simple new continuous-time CMOS comparator circuit with supply-to-supply input common-mode range is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit requires an area of 416 μm×221 μm in a MOSIS 2-micron CMOS technology. It operates at 3 V and requires between 0.5 and 1.3 mA. Delays of between 54 and 282 ns have been measured

Keywords

CMOS analogue integrated circuits; VLSI; comparators (circuits); delays; 0.5 to 1.3 mA; 2 micron; 3 V; 54 to 282 ns; MOSIS CMOS technology; VLSI; continuous-time CMOS comparator circuit; current summing node; delays; parallel complementary decision path; power-supply-valued inputs; supply-to-supply input common-mode range; voltage loads; Built-in self-test; CMOS technology; Circuits; Delay; Power engineering computing; Rail to rail inputs; Railway engineering; Signal design; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.666058

Filename

666058