Time constrained operation of systolic arrays

Partial results of a research project concerning the behaviour of systolic arrays as a function of the number of compute cycles are presented. The array is viewed as a device implementing families of transformations. The transformation implemented are parameterized by the compute cycle. It is shown that arrays designed for a generic algorithm representation may be efficient for special cases. Some realizations can be evaluated in a reduced number of cycles. For real-time applications, the realizations may offer distinctive advantages in throughput. The use of these fast forms in optimal filter design is described. Linear algorithms are discussed in detail. Arrays for matrix multiplication are used as architectures for the evaluation. Conditions for the existence of fast realizations are established