• DocumentCode
    2177483
  • Title

    A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec

  • Author

    Shafique, Muhammad ; Bauer, Lars ; Henkel, Jörg

  • Author_Institution
    Dept. of Embedded Syst., Univ. of Karlsruhe, Karlsruhe
  • fYear
    2009
  • fDate
    20-24 April 2009
  • Firstpage
    1434
  • Lastpage
    1439
  • Abstract
    The H.264/AVC Intra Frame Codec (i.e. all frames are coded as I-frames) targets high-resolution/high-end encoding applications (e.g. digital cinema and high quality archiving etc.), providing much better compression efficiency at lower computational complexity compared to MJPEG2000. Moreover, in case of video coding of very high motion scenes, the number of Intra Macroblocks is dominant. Intra Prediction is a compute intensive and memory-critical part that consumes 80% of the computation time of the entire Intra Compression process when executing the H.264 encoder on MIPS processor. We therefore present a novel hardware for H.264 Intra Prediction that processes all the prediction modes in parallel inside one integrated module (i.e. mode-level parallelism) enabling us to exploit the full space of optimization. It exhibits a group-based write-back scheme to reduce the memory transfers in order to facilitate the fast mode-decision schemes. Our Luma 4times4 hardware is 3.6times, 5.2times, and 5.5times faster than state-of-the-art approaches, QS0, respectively. Our results show that processing Luma 16times16, Chroma 8times8, and Luma 4times4 with the proposed approach is 7.2times, 6.5times, and 1.8times faster (while giving an energy saving of 60%, 80%, and 74%) when compared with Dedicated Module Approach (each prediction mode is processed with its independent hardware module i.e. a typical ASIC style for Intra Prediction). We get an area saving of 58% for Luma 4times4 hardware.
  • Keywords
    data compression; microprocessor chips; video codecs; video coding; H.264/AVC intra frame video codec; Intra Macroblocks; Luma hardware; MIPS processor; compression process; group-based write-back scheme; high performance hardware design; very high motion scenes; video coding; Application specific integrated circuits; Automatic voltage control; Computational complexity; Encoding; Hardware; Layout; Motion pictures; Parallel processing; Video codecs; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
  • Conference_Location
    Nice
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-3781-8
  • Type

    conf

  • DOI
    10.1109/DATE.2009.5090889
  • Filename
    5090889