Performance evaluation of instruction systolic array processors

This paper describes the performance evaluation of an SIMD system on a commonly encountered standard linear equation problem. We introduce a prototype SIMD system, called the Systola 1024; whose parallel architecture is based upon the instruction systolic array concept. To evaluate the performance of this architecture we have implemented an in-cache problem to measure its MFLOP by solving the Gaussian elimination problem to obtain the LU factorization. We also examine the effects of increasing the array processors by a certain factor.