Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance

With shrinking process technologies, the likelihood of mid-life logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in combinatorial logic through the selective addition of redundant logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of logic.