Title :
A single-chip controller for 1.2 Gbps shared buffer ATM switches
Author :
Mizukoshi, Nobuyuki ; Fan, Ruixue ; Suzuki, Hiroshi ; Tomimitsu, Yasuharu ; Sato, Noboru ; Ishida, Hideo ; Ichihara, Michio ; Kirino, Kiyoshi ; Tawada, Makoto ; Nagano, Hiroshi ; Shinohara, Masayuki
Author_Institution :
ULSI Syst. Dev. Labs., NEC Corp., Kawasaki, Japan
Abstract :
A single chip controller for the shared buffer ATM switch with 1.2 Gbps switching capacity has been developed for the first time. Using external standard SRAMs enables low cost implementation of cell buffers, header translation tables and control memories. The chip can support various line interface speeds with standard UTOPIA level 2. High throughput multicast switching capability is achieved by novel buffer control scheme, “re-queuing”. The chip also supports multiple service classes standardized by the ATM forum. The performance of the developed chip is also evaluated
Keywords :
asynchronous transfer mode; buffer circuits; electronic switching systems; microcontrollers; telecommunication control; 1.2 Gbit/s; SRAM; UTOPIA level 2; control memory; header translation table; line interface; multicast switching; multiple service classes; re-queuing; shared buffer ATM switch; single-chip controller; Asynchronous transfer mode; Communication switching; Communication system control; Control systems; Costs; Laboratories; National electric code; Quality of service; Read-write memory; Switches;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606664
