DCT processor architecture based on computation sharing

Author

Kwon, Soonkeon ; Park, Jongsun ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2002

fDate

2002

Firstpage

162

Lastpage

165

Abstract

In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.

Keywords

CMOS digital integrated circuits; data compression; digital arithmetic; digital signal processing chips; discrete cosine transforms; image coding; low-power electronics; multiplying circuits; CMOS standard cell library; DCT processor architecture; computation sharing multiplication; discrete cosine transform processor; hardware complexity; image compression systems; image quality; performance analysis; power consumption reduction; Computational Intelligence Society; Computer architecture; Discrete cosine transforms; Energy consumption; Hardware; Image coding; Image quality; Matrix decomposition; Power engineering computing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on

Print_ISBN

5-7422-0260-1

Type

conf

DOI

10.1109/OCCSC.2002.1029070

Filename

1029070