Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors

Emerging SDR baseband platforms are usually based on multiple DLP+ILP processors with massive parallelism. Although these platforms would theoretically enable advanced SDR signal processing, existing work implemented basic systems and simple algorithms. Importantly, MIMO is not fully supported in most implementations. Implemented MIMO but with a simple linear detector. Our work explores the feasibility for SDR implementations of soft-output ML MIMO detectors, which brings 6-12 dB SNR gains when compared to popular linear detectors. Although soft-output ML MIMO detectors are considered to be challenging even for ASICs, we combine architecture-friendly algorithms, application specific instructions, code transformations and ILP/DLP explorations to make SDR implementations feasible. In our work, a 2times4 ADRES based ASIP with 16-way SIMD can deliver 193 Mbps for 2times2 64 QAM, and 368 Mbps for 2times2 16 QAM transmissions. To the best of our knowledge, this is the first work exploring SDR based soft-output ML MIMO detectors.