ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications

A novel 16-bit flexible application-specific instruction-set processor for an MMSE-IC linear equalizer, used in iterative turbo receiver, is presented in this paper. The proposed ASIP has an SIMD architecture with a specialized instruction-set and 7-stage pipeline control. It supports diverse requirements of MIMO-OFDM wireless standards such as use of QPSK, 16-QAM and 64-QAM modulation in 2times2 and 4times4 spatially multiplexed MIMO-OFDM environment. For these various operational modes, analysis of MMSE-IC LE equations and corresponding complex data representations was conducted. Efficient computational and storage resource sharing is proposed through: (1) matrix register banks (MRB) multiplexing, (2) 16-bit complex arithmetic unit (CAU) comprised of 4 combined complex adder/subtractor/multiplier units, 2 real multipliers, 5 complex adders, and 2 complex subtractors, and (3) flexible 32-bit to 16-bit data conversion at multipliers´ output. With this architecture, the designed ASIP ensures, along with flexibility, high performance in terms of throughput and area. Logic synthesis results reveal a maximum clock frequency of 546 MHz and a total area of 0.37 mm² using 90 nm technology. For 2times2 spatially multiplexed MIMO system, the proposed ASIP achieves a throughput of 273 Msymbol/sec.