• DocumentCode
    2178541
  • Title

    Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication

  • Author

    Seetharam, K. ; Keh, Lance Co Ting ; Nathan, Ralph ; Sorin, Daniel J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2013
  • fDate
    2-4 Dec. 2013
  • Firstpage
    232
  • Lastpage
    235
  • Abstract
    Prior work developed an efficient technique, called reduced precision checking, for detecting errors in floating point addition. In this work, we extend reduced precision checking (RPC) to multiplication. Our results show that RPC can successfully detect errors in floating point multiplication at relatively low cost.
  • Keywords
    error detection; floating point arithmetic; RPC; error detection; floating point multiplication; reduced precision checking artihmetic; Adders; Computational modeling; Floating-point arithmetic; Hardware; Software; Transient analysis; Wires; error detection; fault tolerance; floating point;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Computing (PRDC), 2013 IEEE 19th Pacific Rim International Symposium on
  • Conference_Location
    Vancouver, BC
  • Type

    conf

  • DOI
    10.1109/PRDC.2013.44
  • Filename
    6820870
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2178541