Title :
A 1.5 V CMOS high-speed 16-bit÷8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
Author :
Yeh, C.C. ; Lou, J.H. ; Kuo, J.B.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Based on a 0.8 μm CMOS technology, the speed performance of this 16-bit÷8-bit divider circuit is improved by 45% as compared to the divider using the non-restoring iterative architecture and the domino dynamic logic circuits without the bootstrapped technique
Keywords :
CMOS logic circuits; VLSI; bootstrap circuits; digital arithmetic; dividing circuits; 0.8 micron; 1.5 V; 16 bit; 8 bit; CMOS; divider; low-voltage VLSI; quotient-select architecture; true-single-phase bootstrapped dynamic circuit techniques; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Central Processing Unit; Logic circuits; Low voltage; Parasitic capacitance; Propagation delay; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.666110
