DocumentCode
2178802
Title
A new architecture for area-efficient multiplication by a class of rational coefficients
Author
Schoner, Brian ; Molloy, Stephen
Author_Institution
LSI Logic Corp., Milpitas, CA, USA
Volume
1
fYear
1997
fDate
3-6 Aug 1997
Firstpage
373
Abstract
In this paper we describe a new architecture for the area-efficient realization of a class of fixed-coefficient multipliers, using a recursive algorithm and redundant arithmetic. Difficult coefficients that gain little or no benefit from canonic signed-digit (CSD) or other signed power-of-two (SPT) representations, such as the factor one-third, can be efficiently implemented with a single carry-save addition stage
Keywords
adders; carry logic; digital arithmetic; multiplying circuits; redundancy; area-efficient multiplication; canonic signed-digit representations; carry-save addition stage; rational coefficients; recursive algorithm; redundant arithmetic; signed power-of-two representations; Adders; Arithmetic; Circuits; Digital TV; Digital filters; Discrete cosine transforms; Equations; Hardware; Large scale integration; Logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location
Sacramento, CA
Print_ISBN
0-7803-3694-1
Type
conf
DOI
10.1109/MWSCAS.1997.666112
Filename
666112
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