DocumentCode
2178831
Title
CPU Generated Binary and Ternary Loads for Power Delivery Assessment
Author
Lambert, William ; Ayyanar, Rajapandian
Author_Institution
Arizona State Univ., Chandler
fYear
2007
fDate
29-31 Oct. 2007
Firstpage
3
Lastpage
6
Abstract
CPU generated loads useful for analysis and characterization of microprocessor power delivery networks are described along with potential applications. The loads are generated by a functional microprocessor operating in PLL BYPASS mode.
Keywords
microprocessor chips; power supply circuits; CPU generated load; PLL BYPASS mode; microprocessor power delivery network; Character generation; Circuits; Clocks; Frequency; Microprocessors; Phase locked loops; Power generation; Signal generators; Signal processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2007 IEEE
Conference_Location
Atlanta, GA
Print_ISBN
978-1-4244-0883-2
Type
conf
DOI
10.1109/EPEP.2007.4387108
Filename
4387108
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