Title :
CPU Generated Binary and Ternary Loads for Power Delivery Assessment
Author :
Lambert, William ; Ayyanar, Rajapandian
Author_Institution :
Arizona State Univ., Chandler
Abstract :
CPU generated loads useful for analysis and characterization of microprocessor power delivery networks are described along with potential applications. The loads are generated by a functional microprocessor operating in PLL BYPASS mode.
Keywords :
microprocessor chips; power supply circuits; CPU generated load; PLL BYPASS mode; microprocessor power delivery network; Character generation; Circuits; Clocks; Frequency; Microprocessors; Phase locked loops; Power generation; Signal generators; Signal processing; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2007 IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-0883-2
DOI :
10.1109/EPEP.2007.4387108
