Title :
Modular reduction by multi-level table lookup
Author :
Parhami, Behrooz
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
Common designs for reducing the lookup table size in modular reduction (computing of residues) all require peripheral logic in the form of multiplexers and/or (multi-operand) adders. We derive optimal two-level modular reduction circuits that are synthesized from lookup tables and pipeline latches only. We compare three such purely tabular realizations in terms of total table size. Extensions to more than two lookup levels, for gaining higher throughput, are also briefly discussed
Keywords :
VLSI; function evaluation; iterative methods; pipeline arithmetic; residue number systems; table lookup; lookup table size; multi-level table lookup; optimal two-level modular reduction circuits; pipeline latches; purely tabular realizations; residues; throughput; total table size; Adders; Arithmetic; Circuits; Latches; Logic; Multiplexing; Pipeline processing; Table lookup; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.666114
