Title :
Leading-zero anticipatory logics for fast floating addition with carry propagation signal
Author :
Chang, Tsin-Yuan ; Huang, Jing-Reng ; Yang, Shao-Sheng
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A new leading zero anticipatory logic, that shares the carry propagation signals used in the FLP adder and can look ahead k bits with detailed transistor-level design, is proposed. By VLSI simulations, the area required and delay are reduced by 35% and 19%, respectively, with look-ahead two bits (k=2) compared to Suzuki´s with better prediction
Keywords :
VLSI; adders; carry logic; delays; digital simulation; floating point arithmetic; logic CAD; FLP adder; VLSI simulations; area; carry propagation signal; delay; fast floating addition; leading-zero anticipatory logics; transistor-level design; Adders; Arithmetic; Boolean functions; Circuits; Councils; Equations; Logic design; Propagation delay;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.666115
