A 4*2.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core

This paper reports on a direct sequence spread spectrum (DSSS) ASIC, which integrates all the digital functions of an L-band satellite pager. The ASIC performs digital IQ-downconversion of a carrier up to 10 MHz running from a 40 MHz clock. The maximum chip rate is 4*2.5 Mchip/s. The receiver integrates an ARM6 core, memory, a UART, and flexible DSP hardware. Therefore, it is fully programmable. The use of macrocells and a self timed architecture allowed the design to have an aggressive design time of 7 months from specification to silicon. A low power redesign of the on-chip downconverter and decimator resulted in 45% power savings