Test pattern generation for multiple output digital circuits using cubical calculus and Boolean differences

A new method is presented for generating test patterns for multiple output combinational circuits. Formal mathematical techniques, involving the cubical calculus and Boolean differences, are used to generate test patterns thus dispensing with the costly process of fault simulations. The methods provide the basis for test generation algorithms which are suitable for computer implementation, and also enable testability measures such as observability and controllability, to be computed with relative ease